WOULDN’T IT BE nice if you could stamp out semiconductors like a printing press? Molecular Imprints is making a technology called imprint lithography that lets you do just that, stamp out chips.
The idea is simple, instead of a mask and light source to do lithography in your fab, you make the high tech equivalent of a rubber stamp and stamp out the chips. If it works right, it is cheaper, faster and less prone to defects. Many new technologies make this claim, but imprint lithography (IL) could be one that actually succeeds.
Molecular Imprints (MII) has several of it’s Imprio devices in pre-production, moving to production very soon, so it is quite real. The initial applications are hard drive platter patterning, Hitachi and Fujitsu are the first out of the gate. Toshiba and Sematech are looking at it for semiconductor production as well.
How does it work? The old way is to spin a photoresist onto the wafer, cure parts with patterned light, and remove the rest after. There are a bunch of steps involved, but it is a known and ‘safe’ technology. IL does things very differently, they take the wafer and spray drops of photoresist onto the wafer with the high tech equivalent of an inkjet printer.
Think your ink costs a lot?
The end result is a chip that had drops of photoresist on top. Instead of a mask, the MII device lowers a glass stamp with the patterns you want etched onto the wafer. The imprint does not touch the surface of the chip, it just comes really close, allowing the drops of resist to wick into the grooves via capillary action.
The drops, allignment and mask
The hard part is not the theory, but making sure the masks have groove edges wick the photoresist well, don’t leave air pockets, and in general are perfect. If you think about it, any defect in the imprint gets stamped out again and again and again. The devil is in the details, but MII looks to have exorcised most of those.
Part of the process is aligning the mask right. If you stamp out a perfect pattern a few microns off of where you want, it doesn’t do you much good. The alignment is tricker in this case because you not only have to get it in the right place on three axis (X,Y, and Z/height), but the wafer has to be perfectly flat.
X, Y and Z are perfectly doable optically, but if the wafer is not perfectly planar after being shuttled around, you are in trouble. MII solved this by having pistons that will apply force to the correct areas making sure the die you are working on is dead flat.
Once it is all lined up, the stamp is lowered, the resist wicked into the pattern, an then a UV light is flashed on the back of the stamp. Since it is glass, the resist is cured while the stamp is ‘on’ the wafer. It takes about 1 second to cure, and then off to the next one.
If this sounds like a printing press, you have the right idea. Spray resist, make sure things are lined up, and stamp. Repeat until you get bored or the market is saturated with the widgets you make. Right now, MII is claiming that they can make structures down to about 12nm which should be good enough for the next few years.
Given that the technology appears to be working, HDs made with them should be out in the not so distant future, MII’s future appears bright. If it all works out, IL may make semiconductor production cheaper and more reliable. Keep an eye on this technology.S|A
Latest posts by Charlie Demerjian (see all)
- What’s going on with Qualcomm’s Oryon SoC? - Sep 26, 2023
- What is the code name for the next Qualcomm laptop SoC? - Sep 19, 2023
- How fast is Qualcomm’s Oryon SoC - Sep 19, 2023
- How is Qualcomm’s Oryon SoC doing? - Sep 12, 2023
- A new player enters the ARM laptop SoC space - Aug 16, 2023